1 /** 2 * Compiler implementation of the 3 * $(LINK2 http://www.dlang.org, D programming language). 4 * 5 * Copyright: Copyright (C) ?-2021 by The D Language Foundation, All Rights Reserved 6 * Authors: $(LINK2 http://www.digitalmars.com, Walter Bright) 7 * License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0) 8 * Source: $(LINK2 https://github.com/dlang/dmd/blob/master/src/dmd/backend/xmm.d, backend/_xmm.d) 9 */ 10 11 module dmd.backend.xmm; 12 13 // Online documentation: https://dlang.org/phobos/dmd_backend_xmm.html 14 15 // XMM opcodes 16 17 enum 18 { 19 ADDSS = 0xF30F58, // ADDSS xmm1, xmm2/mem32 F3 0F 58 /r 20 ADDSD = 0xF20F58, // ADDSD xmm1, xmm2/mem64 F2 0F 58 /r 21 ADDPS = 0x000F58, // ADDPS xmm1, xmm2/mem128 0F 58 /r 22 ADDPD = 0x660F58, // ADDPD xmm1, xmm2/mem128 66 0F 58 /r 23 PADDB = 0x660FFC, // PADDB xmm1, xmm2/mem128 66 0F FC /r 24 PADDW = 0x660FFD, // PADDW xmm1, xmm2/mem128 66 0F FD /r 25 PADDD = 0x660FFE, // PADDD xmm1, xmm2/mem128 66 0F FE /r 26 PADDQ = 0x660FD4, // PADDQ xmm1, xmm2/mem128 66 0F D4 /r 27 28 SUBSS = 0xF30F5C, // SUBSS xmm1, xmm2/mem32 F3 0F 5C /r 29 SUBSD = 0xF20F5C, // SUBSD xmm1, xmm2/mem64 F2 0F 5C /r 30 SUBPS = 0x000F5C, // SUBPS xmm1, xmm2/mem128 0F 5C /r 31 SUBPD = 0x660F5C, // SUBPD xmm1, xmm2/mem128 66 0F 5C /r 32 PSUBB = 0x660FF8, // PSUBB xmm1, xmm2/mem128 66 0F F8 /r 33 PSUBW = 0x660FF9, // PSUBW xmm1, xmm2/mem128 66 0F F9 /r 34 PSUBD = 0x660FFA, // PSUBD xmm1, xmm2/mem128 66 0F FA /r 35 PSUBQ = 0x660FFB, // PSUBQ xmm1, xmm2/mem128 66 0F FB /r 36 37 MULSS = 0xF30F59, // MULSS xmm1, xmm2/mem32 F3 0F 59 /r 38 MULSD = 0xF20F59, // MULSD xmm1, xmm2/mem64 F2 0F 59 /r 39 MULPS = 0x000F59, // MULPS xmm1, xmm2/mem128 0F 59 /r 40 MULPD = 0x660F59, // MULPD xmm1, xmm2/mem128 66 0F 59 /r 41 PMULLW = 0x660FD5, // PMULLW xmm1, xmm2/mem128 66 0F D5 /r 42 43 DIVSS = 0xF30F5E, // DIVSS xmm1, xmm2/mem32 F3 0F 5E /r 44 DIVSD = 0xF20F5E, // DIVSD xmm1, xmm2/mem64 F2 0F 5E /r 45 DIVPS = 0x000F5E, // DIVPS xmm1, xmm2mem/128 0F 5E /r 46 DIVPD = 0x660F5E, // DIVPD xmm1, xmm2/mem128 66 0F 5E /r 47 48 PAND = 0x660FDB, // PAND xmm1, xmm2/mem128 66 0F DB /r 49 POR = 0x660FEB, // POR xmm1, xmm2/mem128 66 0F EB /r 50 51 UCOMISS = 0x000F2E, // UCOMISS xmm1, xmm2/mem32 0F 2E /r 52 UCOMISD = 0x660F2E, // UCOMISD xmm1, xmm2/mem64 66 0F 2E /r 53 54 XORPS = 0x000F57, // XORPS xmm1, xmm2/mem128 0F 57 /r 55 XORPD = 0x660F57, // XORPD xmm1, xmm2/mem128 66 0F 57 /r 56 57 // Use STO and LOD instead of MOV to distinguish the direction 58 STOSS = 0xF30F11, // MOVSS xmm1/mem32, xmm2 F3 0F 11 /r 59 STOSD = 0xF20F11, // MOVSD xmm1/mem64, xmm2 F2 0F 11 /r 60 STOAPS = 0x000F29, // MOVAPS xmm1/mem128, xmm2 0F 29 /r 61 STOAPD = 0x660F29, // MOVAPD xmm1/mem128, xmm2 66 0F 29 /r 62 STODQA = 0x660F7F, // MOVDQA xmm1/mem128, xmm2 66 0F 7F /r 63 STOD = 0x660F7E, // MOVD reg/mem64, xmm 66 0F 7E /r 64 STOQ = 0x660FD6, // MOVQ xmm1/mem64, xmm2 66 0F D6 / 65 66 LODSS = 0xF30F10, // MOVSS xmm1, xmm2/mem32 F3 0F 10 /r 67 LODSD = 0xF20F10, // MOVSD xmm1, xmm2/mem64 F2 0F 10 /r 68 LODAPS = 0x000F28, // MOVAPS xmm1, xmm2/mem128 0F 28 /r 69 LODAPD = 0x660F28, // MOVAPD xmm1, xmm2/mem128 66 0F 28 /r 70 LODDQA = 0x660F6F, // MOVDQA xmm1, xmm2/mem128 66 0F 6F /r 71 LODD = 0x660F6E, // MOVD xmm, reg/mem64 66 0F 6E /r 72 LODQ = 0xF30F7E, // MOVQ xmm1, xmm2/mem64 F3 0F 7E /r 73 74 LODDQU = 0xF30F6F, // MOVDQU xmm1, xmm2/mem128 F3 0F 6F /r 75 STODQU = 0xF30F7F, // MOVDQU xmm1/mem128, xmm2 F3 0F 7F /r 76 MOVDQ2Q = 0xF20FD6, // MOVDQ2Q mmx, xmm F2 0F D6 /r 77 MOVHLPS = 0x0F12, // MOVHLPS xmm1, xmm2 0F 12 /r 78 LODHPD = 0x660F16, // MOVHPD xmm, mem64 66 0F 16 /r 79 STOHPD = 0x660F17, // MOVHPD mem64, xmm 66 0F 17 /r 80 LODHPS = 0x0F16, // MOVHPS xmm, mem64 0F 16 /r 81 STOHPS = 0x0F17, // MOVHPS mem64, xmm 0F 17 /r 82 MOVLHPS = 0x0F16, // MOVLHPS xmm1, xmm2 0F 16 /r 83 LODLPD = 0x660F12, // MOVLPD xmm, mem64 66 0F 12 /r 84 STOLPD = 0x660F13, // MOVLPD mem64, xmm 66 0F 13 /r 85 LODLPS = 0x0F12, // MOVLPS xmm, mem64 0F 12 /r 86 STOLPS = 0x0F13, // MOVLPS mem64, xmm 0F 13 /r 87 MOVMSKPD = 0x660F50, // MOVMSKPD reg32, xmm 66 0F 50 /r 88 MOVMSKPS = 0x0F50, // MOVMSKPS reg32, xmm 0F 50 /r 89 MOVNTDQ = 0x660FE7, // MOVNTDQ mem128, xmm 66 0F E7 /r 90 MOVNTI = 0x0FC3, // MOVNTI m32,r32 0F C3 /r 91 // MOVNTI m64,r64 0F C3 /r 92 MOVNTPD = 0x660F2B, // MOVNTPD mem128, xmm 66 0F 2B /r 93 MOVNTPS = 0x0F2B, // MOVNTPS mem128, xmm 0F 2B /r 94 MOVNTQ = 0x0FE7, // MOVNTQ m64, mmx 0F E7 /r 95 MOVQ2DQ = 0xF30FD6, // MOVQ2DQ xmm, mmx F3 0F D6 /r 96 LODUPD = 0x660F10, // MOVUPD xmm1, xmm2/mem128 66 0F 10 /r 97 STOUPD = 0x660F11, // MOVUPD xmm1/mem128, xmm2 66 0F 11 /r 98 LODUPS = 0x0F10, // MOVUPS xmm1, xmm2/mem128 0F 10 /r 99 STOUPS = 0x0F11, // MOVUPS xmm1/mem128, xmm2 0F 11 /r 100 101 PACKSSDW = 0x660F6B, // PACKSSDW xmm1, xmm2/mem128 66 0F 6B /r 102 PACKSSWB = 0x660F63, // PACKSSWB xmm1, xmm2/mem128 66 0F 63 /r 103 PACKUSWB = 0x660F67, // PACKUSWB xmm1, xmm2/mem128 66 0F 67 /r 104 PADDSB = 0x660FEC, // PADDSB xmm1, xmm2/mem128 66 0F EC /r 105 PADDSW = 0x660FED, // PADDSW xmm1, xmm2/mem128 66 0F ED /r 106 PADDUSB = 0x660FDC, // PADDUSB xmm1, xmm2/mem128 66 0F DC /r 107 PADDUSW = 0x660FDD, // PADDUSW xmm1, xmm2/mem128 66 0F DD /r 108 PANDN = 0x660FDF, // PANDN xmm1, xmm2/mem128 66 0F DF /r 109 PCMPEQB = 0x660F74, // PCMPEQB xmm1, xmm2/mem128 66 0F 74 /r 110 PCMPEQD = 0x660F76, // PCMPEQD xmm1, xmm2/mem128 66 0F 76 /r 111 PCMPEQW = 0x660F75, // PCMPEQW xmm1, xmm2/mem128 66 0F 75 /r 112 PCMPGTB = 0x660F64, // PCMPGTB xmm1, xmm2/mem128 66 0F 64 /r 113 PCMPGTD = 0x660F66, // PCMPGTD xmm1, xmm2/mem128 66 0F 66 /r 114 PCMPGTW = 0x660F65, // PCMPGTW xmm1, xmm2/mem128 66 0F 65 /r 115 PMADDWD = 0x660FF5, // PMADDWD xmm1, xmm2/mem128 66 0F F5 /r 116 PSLLW = 0x660FF1, // PSLLW xmm1, xmm2/mem128 66 0F F1 /r 117 // PSLLW xmm, imm8 66 0F 71 /6 ib 118 PSLLD = 0x660FF2, // PSLLD xmm1, xmm2/mem128 66 0F F2 /r 119 // PSLLD xmm, imm8 66 0F 72 /6 ib 120 PSLLQ = 0x660FF3, // PSLLQ xmm1, xmm2/mem128 66 0F F3 /r 121 // PSLLQ xmm, imm8 66 0F 73 /6 ib 122 PSRAW = 0x660FE1, // PSRAW xmm1, xmm2/mem128 66 0F E1 /r 123 // PSRAW xmm, imm8 66 0F 71 /4 ib 124 PSRAD = 0x660FE2, // PSRAD xmm1, xmm2/mem128 66 0F E2 /r 125 // PSRAD xmm, imm8 66 0F 72 /4 ib 126 PSRLW = 0x660FD1, // PSRLW xmm1, xmm2/mem128 66 0F D1 /r 127 // PSRLW xmm, imm8 66 0F 71 /2 ib 128 PSRLD = 0x660FD2, // PSRLD xmm1, xmm2/mem128 66 0F D2 /r 129 // PSRLD xmm, imm8 66 0F 72 /2 ib 130 PSRLQ = 0x660FD3, // PSRLQ xmm1, xmm2/mem128 66 0F D3 /r 131 // PSRLQ xmm, imm8 66 0F 73 /2 ib 132 PSUBSB = 0x660FE8, // PSUBSB xmm1, xmm2/mem128 66 0F E8 /r 133 PSUBSW = 0x660FE9, // PSUBSW xmm1, xmm2/mem128 66 0F E9 /r 134 PSUBUSB = 0x660FD8, // PSUBUSB xmm1, xmm2/mem128 66 0F D8 /r 135 PSUBUSW = 0x660FD9, // PSUBUSW xmm1, xmm2/mem128 66 0F D9 /r 136 PUNPCKHBW = 0x660F68, // PUNPCKHBW xmm1, xmm2/mem128 66 0F 68 /r 137 PUNPCKHDQ = 0x660F6A, // PUNPCKHDQ xmm1, xmm2/mem128 66 0F 6A /r 138 PUNPCKHWD = 0x660F69, // PUNPCKHWD xmm1, xmm2/mem128 66 0F 69 /r 139 PUNPCKLBW = 0x660F60, // PUNPCKLBW xmm1, xmm2/mem128 66 0F 60 /r 140 PUNPCKLDQ = 0x660F62, // PUNPCKLDQ xmm1, xmm2/mem128 66 0F 62 /r 141 PUNPCKLWD = 0x660F61, // PUNPCKLWD xmm1, xmm2/mem128 66 0F 61 /r 142 PXOR = 0x660FEF, // PXOR xmm1, xmm2/mem128 66 0F EF /r 143 ANDPD = 0x660F54, // ANDPD xmm1, xmm2/mem128 66 0F 54 /r 144 ANDPS = 0x0F54, // ANDPS xmm1, xmm2/mem128 0F 54 /r 145 ANDNPD = 0x660F55, // ANDNPD xmm1, xmm2/mem128 66 0F 55 /r 146 ANDNPS = 0x0F55, // ANDNPS xmm1, xmm2/mem128 0F 55 /r 147 CMPPS = 0x0FC2, // CMPPS xmm1, xmm2/mem128, imm8 0F C2 /r ib 148 CMPPD = 0x660FC2, // CMPPD xmm1, xmm2/mem128, imm8 66 0F C2 /r ib 149 CMPSD = 0xF20FC2, // CMPSD xmm1, xmm2/mem64, imm8 F2 0F C2 /r ib 150 CMPSS = 0xF30FC2, // CMPSS xmm1, xmm2/mem32, imm8 F3 0F C2 /r ib 151 COMISD = 0x660F2F, // COMISD xmm1, xmm2/mem64 66 0F 2F /r 152 COMISS = 0x0F2F, // COMISS xmm1, xmm2/mem32 0F 2F /r 153 CVTDQ2PD = 0xF30FE6, // CVTDQ2PD xmm1, xmm2/mem64 F3 0F E6 /r 154 CVTDQ2PS = 0x0F5B, // CVTDQ2PS xmm1, xmm2/mem128 0F 5B /r 155 CVTPD2DQ = 0xF20FE6, // CVTPD2DQ xmm1, xmm2/mem128 F2 0F E6 /r 156 CVTPD2PI = 0x660F2D, // CVTPD2PI mmx, xmm2/mem128 66 0F 2D /r 157 CVTPD2PS = 0x660F5A, // CVTPD2PS xmm1, xmm2/mem128 66 0F 5A /r 158 CVTPI2PD = 0x660F2A, // CVTPI2PD xmm, mmx/mem64 66 0F 2A /r 159 CVTPI2PS = 0x0F2A, // CVTPI2PS xmm, mmx/mem64 0F 2A /r 160 CVTPS2DQ = 0x660F5B, // CVTPS2DQ xmm1, xmm2/mem128 66 0F 5B /r 161 CVTPS2PD = 0x0F5A, // CVTPS2PD xmm1, xmm2/mem64 0F 5A /r 162 CVTPS2PI = 0x0F2D, // CVTPS2PI mmx, xmm/mem64 0F 2D /r 163 CVTSD2SI = 0xF20F2D, // CVTSD2SI reg32, xmm/mem64 F2 0F 2D /r 164 // CVTSD2SI reg64, xmm/mem64 F2 0F 2D /r 165 CVTSD2SS = 0xF20F5A, // CVTSD2SS xmm1, xmm2/mem64 F2 0F 5A /r 166 CVTSI2SD = 0xF20F2A, // CVTSI2SD xmm, reg/mem32 F2 0F 2A /r 167 // CVTSI2SD xmm, reg/mem64 F2 0F 2A /r 168 CVTSI2SS = 0xF30F2A, // CVTSI2SS xmm, reg/mem32 F3 0F 2A /r 169 // CVTSI2SS xmm, reg/mem64 F3 0F 2A /r 170 CVTSS2SD = 0xF30F5A, // CVTSS2SD xmm1, xmm2/mem32 F3 0F 5A /r 171 CVTSS2SI = 0xF30F2D, // CVTSS2SI reg32, xmm2/mem32 F3 0F 2D /r 172 // CVTSS2SI reg64, xmm2/mem32 F3 0F 2D /r 173 CVTTPD2PI = 0x660F2C, // CVTPD2PI mmx, xmm/mem128 66 0F 2C /r 174 CVTTPD2DQ = 0x660FE6, // CVTTPD2DQ xmm1, xmm2/mem128 66 0F E6 /r 175 CVTTPS2DQ = 0xF30F5B, // CVTTPS2DQ xmm1, xmm2/mem128 F3 0F 5B /r 176 CVTTPS2PI = 0x0F2C, // CVTTPS2PI mmx xmm/mem64 0F 2C /r 177 CVTTSD2SI = 0xF20F2C, // CVTTSD2SI reg32, xmm/mem64 F2 0F 2C /r 178 // CVTTSD2SI reg64, xmm/mem64 F2 0F 2C /r 179 CVTTSS2SI = 0xF30F2C, // CVTTSS2SI reg32, xmm/mem32 F3 0F 2C /r 180 // CVTTSS2SI reg64, xmm/mem32 F3 0F 2C /r 181 MASKMOVDQU = 0x660FF7, // MASKMOVDQU xmm1, xmm2 66 0F F7 /r 182 MASKMOVQ = 0x0FF7, // MASKMOVQ mm1,mm2 0F F7 /r 183 MAXPD = 0x660F5F, // MAXPD xmm1, xmm2/mem128 66 0F 5F /r 184 MAXPS = 0x0F5F, // MAXPS xmm1, xmm2/mem128 0F 5F /r 185 MAXSD = 0xF20F5F, // MAXSD xmm1, xmm2/mem64 F2 0F 5F /r 186 MAXSS = 0xF30F5F, // MAXSS xmm1, xmm2/mem32 F3 0F 5F /r 187 MINPD = 0x660F5D, // MINPD xmm1, xmm2/mem128 66 0F 5D /r 188 MINPS = 0x0F5D, // MINPS xmm1, xmm2/mem128 0F 5D /r 189 MINSD = 0xF20F5D, // MINSD xmm1, xmm2/mem64 F2 0F 5D /r 190 MINSS = 0xF30F5D, // MINSS xmm1, xmm2/mem32 F3 0F 5D /r 191 ORPD = 0x660F56, // ORPD xmm1, xmm2/mem128 66 0F 56 /r 192 ORPS = 0x0F56, // ORPS xmm1, xmm2/mem128 0F 56 /r 193 PAVGB = 0x660FE0, // PAVGB xmm1, xmm2/mem128 66 0F E0 /r 194 PAVGW = 0x660FE3, // PAVGW xmm1, xmm2/mem128 66 0F E3 /r 195 PMAXSW = 0x660FEE, // PMAXSW xmm1, xmm2/mem128 66 0F EE / 196 PINSRW = 0x660FC4, // PINSRW xmm, reg32/mem16, imm8 66 0F C4 /r ib 197 PMAXUB = 0x660FDE, // PMAXUB xmm1, xmm2/mem128 66 0F DE /r 198 PMINSW = 0x660FEA, // PMINSW xmm1, xmm2/mem128 66 0F EA /r 199 PMINUB = 0x660FDA, // PMINUB xmm1, xmm2/mem128 66 0F DA /r 200 PMOVMSKB = 0x660FD7, // PMOVMSKB reg32, xmm 66 0F D7 /r 201 PMULHUW = 0x660FE4, // PMULHUW xmm1, xmm2/mem128 66 0F E4 /r 202 PMULHW = 0x660FE5, // PMULHW xmm1, xmm2/mem128 66 0F E5 / 203 PMULUDQ = 0x660FF4, // PMULUDQ xmm1, xmm2/mem128 66 0F F4 /r 204 PSADBW = 0x660FF6, // PSADBW xmm1, xmm2/mem128 66 0F F6 /r 205 PUNPCKHQDQ = 0x660F6D, // PUNPCKHQDQ xmm1, xmm2/mem128 66 0F 6D /r 206 PUNPCKLQDQ = 0x660F6C, // PUNPCKLQDQ xmm1, xmm2/mem128 66 0F 6C /r 207 RCPPS = 0x0F53, // RCPPS xmm1, xmm2/mem128 0F 53 /r 208 RCPSS = 0xF30F53, // RCPSS xmm1, xmm2/mem32 F3 0F 53 /r 209 RSQRTPS = 0x0F52, // RSQRTPS xmm1, xmm2/mem128 0F 52 /r 210 RSQRTSS = 0xF30F52, // RSQRTSS xmm1, xmm2/mem32 F3 0F 52 /r 211 SQRTPD = 0x660F51, // SQRTPD xmm1, xmm2/mem128 66 0F 51 /r 212 SHUFPD = 0x660FC6, // SHUFPD xmm1, xmm2/mem128, imm8 66 0F C6 /r ib 213 SHUFPS = 0x0FC6, // SHUFPS xmm1, xmm2/mem128, imm8 0F C6 /r ib 214 SQRTPS = 0x0F51, // SQRTPS xmm1, xmm2/mem128 0F 51 /r 215 SQRTSD = 0xF20F51, // SQRTSD xmm1, xmm2/mem64 F2 0F 51 /r 216 SQRTSS = 0xF30F51, // SQRTSS xmm1, xmm2/mem32 F3 0F 51 /r 217 UNPCKHPD = 0x660F15, // UNPCKHPD xmm1, xmm2/mem12866 0F 15 /r 218 UNPCKHPS = 0x0F15, // UNPCKHPS xmm1, xmm2/mem1280F 15 /r 219 UNPCKLPD = 0x660F14, // UNPCKLPD xmm1, xmm2/mem128 66 0F 14 /r 220 UNPCKLPS = 0x0F14, // UNPCKLPS xmm1, xmm2/mem1280F 14 /r 221 222 PSHUFD = 0x660F70, // PSHUFD xmm1, xmm2/mem128, imm8 66 0F 70 /r ib 223 PSHUFHW = 0xF30F70, // PSHUFHW xmm1, xmm2/mem128, imm8 F3 0F 70 /r ib 224 PSHUFLW = 0xF20F70, // PSHUFLW xmm1, xmm2/mem128, imm8 F2 0F 70 /r ib 225 PSHUFW = 0x0F70, // PSHUFW mm1, mm2/mem64, imm8 0F 70 /r ib 226 PSLLDQ = 0x07660F73, // PSLLDQ xmm, imm8 66 0F 73 /7 ib 227 PSRLDQ = 0x03660F73, // PSRLDQ xmm, imm8 66 0F 73 /3 ib 228 229 PREFETCH = 0x0F18, 230 231 PEXTRW = 0x660FC5, // PEXTRW reg32, xmm, imm8 66 0F C5 /r ib 232 STMXCSR = 0x0FAE, // STMXCSR mem32 0F AE /3 233 234 // SSE3 Pentium 4 (Prescott) 235 236 ADDSUBPD = 0x660FD0, // ADDSUBPD xmm1, xmm2/m128 237 ADDSUBPS = 0xF20FD0, 238 HADDPD = 0x660F7C, 239 HADDPS = 0xF20F7C, 240 HSUBPD = 0x660F7D, 241 HSUBPS = 0xF20F7D, 242 MOVDDUP = 0xF20F12, 243 MOVSHDUP = 0xF30F16, 244 MOVSLDUP = 0xF30F12, 245 LDDQU = 0xF20FF0, 246 MONITOR = 0x0F01C8, 247 MWAIT = 0x0F01C9, 248 249 // SSSE3 250 PALIGNR = 0x660F3A0F, 251 PHADDD = 0x660F3802, 252 PHADDW = 0x660F3801, 253 PHADDSW = 0x660F3803, 254 PABSB = 0x660F381C, 255 PABSD = 0x660F381E, 256 PABSW = 0x660F381D, 257 PSIGNB = 0x660F3808, 258 PSIGND = 0x660F380A, 259 PSIGNW = 0x660F3809, 260 PSHUFB = 0x660F3800, 261 PMADDUBSW = 0x660F3804, 262 PMULHRSW = 0x660F380B, 263 PHSUBD = 0x660F3806, 264 PHSUBW = 0x660F3805, 265 PHSUBSW = 0x660F3807, 266 267 // SSE4.1 268 // See Intel SSE4 Programming Reference 269 270 BLENDPD = 0x660F3A0D, // 66 0F 3A 0D /r ib BLENDPD xmm1, xmm2/m128, imm8 271 BLENDPS = 0x660F3A0C, // 66 0F 3A 0C /r ib BLENDPS xmm1, xmm2/m128, imm8 272 BLENDVPD = 0x660F3815, // 66 0F 38 15 /r BLENDVPD xmm1, xmm2/m128, <XMM0> 273 BLENDVPS = 0x660F3814, // 66 0F 38 14 /r BLENDVPS xmm1, xmm2/m128, <XMM0> 274 DPPD = 0x660F3A41, 275 DPPS = 0x660F3A40, 276 EXTRACTPS = 0x660F3A17, 277 INSERTPS = 0x660F3A21, 278 MPSADBW = 0x660F3A42, 279 PBLENDVB = 0x660F3810, 280 PBLENDW = 0x660F3A0E, 281 PEXTRD = 0x660F3A16, 282 PEXTRQ = 0x660F3A16, 283 PINSRB = 0x660F3A20, // 66 0F 3A 20 /r ib PINSRB xmm1, r32/m8, imm8 284 PINSRD = 0x660F3A22, 285 PINSRQ = 0x660F3A22, 286 287 MOVNTDQA = 0x660F382A, 288 PACKUSDW = 0x660F382B, 289 PCMPEQQ = 0x660F3829, 290 PEXTRB = 0x660F3A14, // 66 0F 3A 14 /r ib PEXTRB r32/m8, xmm2, imm8 291 // 66 REX.W 0F 3A 14 /r ib PEXTRB r64/m8, xmm2, imm8 292 PHMINPOSUW = 0x660F3841, // 66 0F 38 41 /r PHMINPOSUW xmm1, xmm2/m128 293 PMAXSB = 0x660F383C, 294 PMAXSD = 0x660F383D, 295 PMAXUD = 0x660F383F, 296 PMAXUW = 0x660F383E, 297 PMINSB = 0x660F3838, 298 PMINSD = 0x660F3839, 299 PMINUD = 0x660F383B, 300 PMINUW = 0x660F383A, 301 PMOVSXBW = 0x660F3820, 302 PMOVSXBD = 0x660F3821, 303 PMOVSXBQ = 0x660F3822, 304 PMOVSXWD = 0x660F3823, 305 PMOVSXWQ = 0x660F3824, 306 PMOVSXDQ = 0x660F3825, 307 PMOVZXBW = 0x660F3830, 308 PMOVZXBD = 0x660F3831, 309 PMOVZXBQ = 0x660F3832, 310 PMOVZXWD = 0x660F3833, 311 PMOVZXWQ = 0x660F3834, 312 PMOVZXDQ = 0x660F3835, 313 PMULDQ = 0x660F3828, 314 PMULLD = 0x660F3840, 315 PTEST = 0x660F3817, // 66 0F 38 17 /r PTEST xmm1, xmm2/m128 316 317 ROUNDPD = 0x660F3A09, // 66 0F 3A 09 /r ib ROUNDPD xmm1, xmm2/m128, imm8 318 ROUNDPS = 0x660F3A08, 319 ROUNDSD = 0x660F3A0B, 320 ROUNDSS = 0x660F3A0A, 321 322 // SSE4.2 323 PCMPESTRI = 0x660F3A61, 324 PCMPESTRM = 0x660F3A60, 325 PCMPISTRI = 0x660F3A63, 326 PCMPISTRM = 0x660F3A62, 327 PCMPGTQ = 0x660F3837, 328 // CRC32 329 330 // SSE4a (AMD only) 331 // EXTRQ,INSERTQ,MOVNTSD,MOVNTSS 332 333 // POPCNT and LZCNT (have their own CPUID bits) 334 POPCNT = 0xF30FB8, 335 // LZCNT 336 337 // AVX 338 XGETBV = 0x0F01D0, 339 XSETBV = 0x0F01D1, 340 VBROADCASTSS = 0x660F3818, 341 VBROADCASTSD = 0x660F3819, 342 VBROADCASTF128 = 0x660F381A, 343 VINSERTF128 = 0x660F3A18, 344 345 // AVX2 346 VPBROADCASTB = 0x660F3878, 347 VPBROADCASTW = 0x660F3879, 348 VPBROADCASTD = 0x660F3858, 349 VPBROADCASTQ = 0x660F3859, 350 VBROADCASTI128 = 0x660F385A, 351 VINSERTI128 = 0x660F3A38, 352 353 // AES 354 AESENC = 0x660F38DC, 355 AESENCLAST = 0x660F38DD, 356 AESDEC = 0x660F38DE, 357 AESDECLAST = 0x660F38DF, 358 AESIMC = 0x660F38DB, 359 AESKEYGENASSIST = 0x660F3ADF, 360 }